1. Field of the Invention
This invention in general relates to a method for forming a gate on a substrate in manufacturing semiconductor devices and more particularly, to a method for forming a gate with a controlled critical dimension and good gate oxide quality.
2. Description of the Related Art
In conventional method for forming a gate on a substrate in manufacturing semiconductor devices, large-grain polysilicon is employed as a gate material. Because the surface of the layer formed by the large-grain polysilicon is very rough due to the size of the grain of the polysilicon, deep UV exposure light is scattered when the polysilicon layer is patterned to form gates. In this case, the critical dimension of the gate is difficult to control, the uniformity thereof cannot be obtained and therefore, a kink effect occurs.
As a resolution of the above problem encountered in the conventional method, employment of amorphous silicon as a gate material on a substrate for manufacturing semiconductor devices is proposed. Since the surface of the layer formed by the amorphous silicon is smoother than that of large-grain polysilicon, a good critical dimension and uniformity of the gate can be obtained. However, in the subsequent thermal processes, the amorphous silicon re-crystallizes at an elevated temperature to form large-grain polysilicon in, for example, cylindrical shapes. Because of the thus-formed large-grain polysilicon, a channeling effect occurs at the interface between the polysilicon gate and the gate oxide layer. This results in penetration of conductive ions, for example N-type ion dopants or P-type ion dopants, and especially boron ions, through the large-grain polysilicon into the gate oxide.
Therefore, it is desired that a method be developed for forming a gate on a substrate, which method can control the critical dimension of the gate and uniformity thereof and simultaneously eliminate the channeling effect between the gate and gate oxide thereon.